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GENLINX TMII GS9035A
Serial Digital Reclocker
DATA SHEET FEATURES * adjustment-free operation * auto-rate selection for 5 SMPTE data rates: 143, 177, 270, 360, 540Mb/s * data rate indication output * serial data output mute when PLL is not locked * immune to harmonic locking * operation independent of SAV/EAV sync signals * low jitter, low power * single external VCO resistor for operation with five input data rates * large input jitter tolerance: typically 0.45 UI beyond loop bandwidth * power savings mode (output serial clock disable) * system friendly: serial clock remains active when data outputs muted * robust lock detect * Pb-free and Green APPLICATIONS The GS9035A is used for Clock and Data recovery, and Jitter elimination for all high speed serial digital interface applications involving SMPTE 259M and other data standards. ORDERING INFORMATION
PART NUMBER GS9035ACPJ GS9035ACTJ GS9035ACPJE3 GS9035ACTJE3 PACKAGE 28 pin PLCC 28 pin PLCC Tape 28 pin PLCC 28 pin PLCC Tape TEMPERATURE 0C to 70C 0C to 70C 0C to 70C 0C to 70C Pb-FREE AND GREEN No No Yes Yes
DESCRIPTION The GS9035A is a high performance clock and data recovery IC designed for serial digital data. The GS9035A receives either single-ended or differential PECL data and outputs differential PECL clock and retimed data signals. The GS9035A can operate in either auto or manual rate selection mode. In auto mode the GS9035A is ideal for multi-rate serial data protocols such as SMPTE 259M. In this mode the GS9035A automatically detects and locks onto the incoming data signal. For single rate data systems, the GS9035A can be configured to operate in manual mode. In both modes, the GS9035A requires only one external resistor to set the VCO centre frequency and provides adjustment-free operation. The GS9035A has dedicated pins to indicate LOCK and data rate. In addition, an internal muting function forces the serial data outputs to a static state when input data is not present or when the PLL is not locked. The serial clock outputs can also be disabled resulting in a 10% power savings. The GS9035A is packaged in a 28 pin PLCC and operates from a single +5 or -5 volt power supply.
GS9035A
COSC
CARRIER DETECT PHASELOCK HARMONIC LOGIC
LOCK
SDO FREQUENCY ACQUISITION
2
SDO PHASE DETECTOR CLK_EN SCO SCO DIVISION 3 BIT COUNTER SMPTE AUTO/MAN
DDI/DDI
CHARGE PUMP
VCO
DECODER
SSO SS1 SS2
LF+ LFS LF-
CBG
RVCO
BLOCK DIAGRAM
Revision Date: June 2004 GENNUM CORPORATION P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3 Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 E-mail: info@gennum.com www.gennum.com Document No. 522 - 41 - 08
ABSOLUTE MAXIMUM RATINGS
PARAMETER Supply Voltage (VS) Input Voltage Range (any input) Operating Temperature Range Storage Temperature Range Lead Temperature (soldering, 10 sec) VALUE 5.5V VCC + 0.5 to VEE - 0.5V 0C TA 70C -65C TS 150C 260C
GS9035A
DC ELECTRICAL CHARACTERISTICS
VCC = 5.0V, VEE = 0V, TA = 0 - 70C unless otherwise stated, RLF = 1.8K, CLF1 = 15nF, CLF2 = 3.3pF.
PARAMETER Supply Voltage Supply Current
CONDITION
MIN 4.75
TYPICAL 5.00 90 105
1
MAX 5.25 110 120 VCC - (VDIFF/2) 2000 0.8 0.8 0.4 -
UNITS V mA mA V mV V
NOTES
TEST LEVEL 3 3 3
CLK_EN = 0 CLK_EN = 1
VEE + (VDIFF/2) 200
DDI/DDI Common Mode Input Voltage Range DDI/DDI Differential Input Drive AUTO/MAN, SMPTE High Low CLK_EN Input Voltage High Low LOCK Output Low Voltage SS{2:0} Output Voltage
0.4 to 4.6 800 0.25 4.8
2
3 3 3
2.0 2.5 4.4
V
3
OH = 500A HIGH, OH = -180A, Auto Mode
LOW, OL = 600A, Auto Mode
V V
3
1 1
-
0.3
0.4
SS{2:0} Input Voltage
HIGH, Manual Mode LOW, ManualMode
2 TEST LEVELS
26
0.8 55
V
3
CLK_EN Source Current NOTES
Low, VIL = 0V
A
1
1. TYPICAL - measured on EB-RD35A board. 2. VDIFF is the differential input signal swing. 3. LOCK is an open collector output and requires an external pull-up resistor. 4. Pins SS[2:0] are outputs in AUTO mode and inputs in MANUAL mode.
1. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges. 2. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges using correlated test. 3. Production test at room temperature and nominal supply voltage. 4. QA sample test. 5. Calculated result based on Level 1,2, or 3. 6. Not tested. Guaranteed by design simulations. 7. Not tested. Based on characterization of nominal parts.
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AC ELECTRICAL CHARACTERISTICS
VCC = 5.0V, VEE = 0V, TA = 0 - 70C unless otherwise stated, RLF = 1.8K, CLF1 = 15nF, CLF2 = 3.3pF
PARAMETER Serial Data Rate Intrinsic Jitter Psuedorandom (2 Intrinsic Jitter Pathological (SDI checkfield) Input Jitter Tolerance
23
CONDITION SDI 270Mb/s - 1) 540Mb/s 270Mb/s 360Mb/s 540Mb/s 270Mb/s 540Mb/s
MIN 143 0.40 0.35 0.5 -200
TYPICAL1 185 164 462 308 260 0.56 0.43 1 1 4 10 1 0 800 300
MAX 540 See Figure 6
UNITS Mb/s ps p-p
NOTES
TEST LEVEL 3
2
4
GS9035A
See Figure 7
ps p-p
2
3
2 200 1000 400
UI p-p
3
9
Lock Time Synchronous Switch
tSWITCH < 0.5s, 270Mb/s 0.5s < tSWITCH < 10ms tSWITCH > 10ms
s ms ms ms s ps mV p-p ps
4
7
Lock Time Asynchronous Switch SDO MUTE Time SDO to SCO Synchronization SDO, SCO Output Signal Swing SDO, SCO Rise and Fall Times NOTES
Loop Bandwidth = 6MHz at 540 Mb/s
5 6
7 7 7 1 7
75 DC load 20% - 80%
600 200
1. TYPICAL - measured on EB-RD35A board, TA = 25C. 2. Characterized 6 sigma rms. 3. IJT measured with sinusoidal modulation beyond Loop Bandwidth (at 6.5MHz). 4. Synchronous switching refers to switching the input data from one source to another source which is at the same data rate (ie: line 10 switching for component NTSC). 5. Asynchronous switching refers to switching the input data from one source to another source which is at a different data rate. 6. SDO MUTE Time refers to the response of the SDO output from valid re-clocked input data to mute mode when the input signal is removed. TEST LEVEL 1. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges. 2. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges using correlated test. 3. Production test at room temperature and nominal supply voltage. 4. QA sample test. 5. Calculated result based on Level 1,2, or 3. 6. Not tested. Guaranteed by design simulations. 7. Not tested. Based on characterization of nominal parts. 8. Not tested. Based on existing design/characterization data of similar product. 9. Indirect test
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TEKTRONIX GIGABERT 1400 CLK DATA
DI DI
GENNUM TEST BOARD SDO
TEKTRONIX CH-1 TRIG CSA803
GS9035A
PATTERN 223-1
Fig. 1 Jitter Measurement Test Setup
PIN CONNECTIONS
CLK_EN SMPTE COSC LOCK VCC3 26 25 24 23 GS9035A TOP VIEW 22 21 20 19 13 LFS 14 LF15 RVCO_RTN 16 RVCO 17 CBG 18 VCC2 SDO SDO SCO SCO SSO SS1 SS2
VEE
4 DDI DDI VEE VEE VCC1 AUTO/MAN VEE 5 6 7 8 9 10 11 12 LF+
3
2
1
28
27
PIN DESCRIPTIONS
NUMBER 1,7,8,11,27 2 3 SYMBOL VEE COSC LOCK TYPE I I O Most negative power supply connection. Timing control capacitor for internal system clock. Lock indication. When HIGH, the GS9035A is locked. LOCK is an open collector output and requires an external 10k pullup resistor. SMPTE/Other rate select. Digital data input (Differential ECL/PECL). Most positive power supply connection. Auto or Manual mode select. TTL/CMOS compatible input. Loop filter component connection. Loop filter component connection. Loop filter component connection. RVCO return. DESCRIPTION
4 5, 6 9 10 12 13 14 15
SMPTE DDI/DDI VCC1 AUTO/MAN LF+ LFS LFRVCO_RTN
I I I I I I I I
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PIN DESCRIPTIONS (continued)
NUMBER 16 17 18 19 - 21 SYMBOL RVCO CBG VCC2 SS[2:0] TYPE I I I I/O Frequency setting resistor. Internal bandgap voltage filter capacitor. Most positive power supply connection. DESCRIPTION
GS9035A
Data rate indication (Auto mode) or data rate select (Manual mode). TTL/CMOS compatible I/O. In auto mode these pins can be left unconnected. Serial clock output. SCO/SCO are differential current mode outputs and require external 75 pullup resistors. Serial data output. SDO/SDO are differential current mode outputs and require external 75 pullup resistors. Most positive power supply connection. Clock enable. When HIGH, the serial clock outputs are enabled.
22, 23
SCO/SCO
O
24, 25
SDO/SDO
O
26 28
VCC3 CLK_EN
I I
TYPICAL PERFORMANCE CURVES
(VS = 5V, TA = 25C unless otherwise shown.)
Fig. 2 Intrinsic Jitter (2 -1 Pattern) 30Mb/s
23
Fig. 4 Intrinsic Jitter (2 -1 Pattern) 270Mb/s
23
Fig. 3 Intrinsic Jitter (2 -1 Pattern) 143Mb/s
23
Fig. 5 Intrinsic Jitter (223-1 Pattern) 540Mb/s
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2000 1800 1600 1400
0.600
143Mb/s
0.550 0.500 0.450
177Mb/s 270Mb/s 360Mb/s
JITTER (ps)
1200
IJT (UI)
1000 800 600 Typical Range, Characterized 400 200 0 100 200 300 400 500 Max Typical Min 600
0.400 0.350 0.300 0.250 0.200
540Mb/s
GS9035A
0
10
20
30
40
50
60
70
SDI DATA RATE (Mb/s)
TA=0 to 70C, VCC=4.75 to 5.25V for the typical range
TEMPERATURE (C)
Fig. 9 Typical IJT vs. Temperature (VCC=5.0V) (Characterized)
Fig. 6 Intrinsic Jitter - Pseudorandom (2
2000 1800 1600 1400
23
-1)
DETAILED DESCRIPTION The GS9035A receives either a single-ended or differential PECL serial data stream at the DDI and DDI inputs. It locks an internal clock to the incoming data and outputs the differential PECL retimed data signal and recovered clock on outputs SDO/SDO and SCO/SCO respectively. The timing between the input, output, and clock signals is shown below.
Max Typical Min Typical Range, Characterized 0 100 200 300 400 500 600
JITTER (ps p-p)
1200 1000 800 600 400 200
DDI
SDO
SDI DATA RATE (Mb/s)
TA = 0 to 70C, VCC = 4.75 to 5.25V for the typical range
SCO
Fig. 7 Intrinsic Jitter - Pathological SDI Checkfield
50%
0.6
Fig. 10 Input/Output Clock Signal Timing
0.5
0.4
The GS9035A reclocker contains four main functional blocks: the Phase Locked Loop, Auto/Manual Data Rate Select, Frequency Acquisition, and Logic Circuit.
1. PHASE LOCKED LOOP (PLL)
IJT (UI)
0.3
0.2
0.1
The Phase Locked Loop locks the internal PLL clock to the incoming data rate. A simplified block diagram of the PLL is shown below. The main components are the VCO, the phase detector, the charge pump, and the loop filter.
100 200 300 400 500 600
0
DATA RATE (Mb/s)
TA = 0 to 70C, VCC = 4.75 to 5.25V
Fig. 8 Typical Input Jitter Tolerance (Characterized)
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DDI/DDI
2 PHASE DETECTOR INTERNAL PLL CLOCK DIVISION
The VCO and an internal divider generate the PLL clock. Divider moduli of 1, 2, and 4 allow the PLL to lock to data rates from 143Mb/s to 540Mb/s. The divider modulus is set by the AUTO/MAN, SMPTE, and SS[2:0] pin (see Auto/Manual Data Rate Select section for further details). In addition, a manually selectable modulus 8 divider allows operation at data rates as low as 30Mb/s.
GS9035A
CHARGE PUMP LF+ LFS LFLOOP FILTER
VCO
When the input data stream is removed for an excessive period of time (see AC electrical characteristics table), the VCO frequency can drift from the previously locked frequency up to the maximum shown in Table 1.
RVCO
TABLE 1: Frequency Drift Range (when PLL loses lock) LOSES LOCK FROM 143Mb/s lock 177Mb/s lock MIN (%) -21 -12 -13 -13 -13 MAX(%) 21 26 28 24 28
RLF CLF1 CLF2
Fig. 11 Simplified Diagram of the PLL 270Mb/s lock 1.1 VCO 360 Mb/s lock 540 Mb/s lock
The VCO is a differential low phase noise, factory trimmed design that provides increased immunity to PCB noise and precise control of the VCO center frequency. The VCO operates between 30 and 540Mb/s and has a pull range of -13 +25% about the center frequency depending on the signal data rate. A single low impedance external resistor, RVCO, sets the VCO center frequency (see Figure 12). The low impedance RVCO minimizes thermal noise and reduces the PLL's sensitivity to PCB noise. For a given RVCO value, the VCO can oscillate at one of two frequencies. When SMPTE = SS0 = logic 1, the VCO center frequency corresponds to the L curve. For all other SMPTE/SS0 combinations, the VCO center frequency corresponds to the H curve (H is approximately 1.5 x L).
800 700
1.2 Phase Detector
The phase detector compares the phase of the PLL clock with the phase of the incoming data signal and generates error correcting timing pulses. The phase detector design provides a linear transfer function between the input phase and output timing pulses maximizing the input jitter tolerance of the PLL.
1.3 Charge Pump
VCO FREQUENCY (MHz)
The charge pump takes the phase detector output timing pulses and creates a charge packet that is proportional to the system phase error. A unique differential charge pump design ensures that the output phase does not drift when data transitions are sparse. This makes the GS9035A ideal for SMPTE 259M applications where pathological signals have data transition densities of 0.05.
1.4 Loop Filter
600 500 400 300 200 100 0 0 200 400 600 800 1000 1200 1400 1600 1800
H
L SMPTE=1 SSO=1
The loop filter integrates the charge pump packets and produces a VCO control voltage. The loop filter is comprised of three external components which are connected to pins LF+, LFS, and LF-. The loop filter design is fully differential giving the GS9035A increased immunity to PCB board noise. The loop filter components are critical in determining the loop bandwidth and damping of the PLL. Choosing these component values is discussed in detail in the PLL Design Guidelines section. Recommended values for SMPTE 259M applications are shown in the Typical Application Circuit diagram.
RVCO ()
Fig. 12 VCO Frequency vs. RVCO
The recommended RVCO value for auto rate SMPTE 259M applications is 365.
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2. FREQUENCY ACQUISITION
4. AUTO/MANUAL DATA RATE SELECT
The core PLL is able to lock if the incoming data rate and the PLL clock frequency are within the PLL capture range (which is slightly larger than the loop bandwidth). To assist the PLL to lock to data rates outside of the capture range, the GS9035A uses a frequency acquisition circuit. The frequency acquisition circuit sweeps the VCO control voltage such that the VCO frequency changes from -10% to +10% of the center frequency. Figure 13 shows a typical sweep waveform.
tswp tsys
The GS9035A can operate in either auto or manual data rate select mode. The mode of operation is selected by a single input pin (AUTO/MAN).
4.1 Auto Mode (AUTO/MAN = 1)
In auto mode, the GS9035A uses a 3-bit counter to automatically cycle through five (SMPTE=1) or three (SMPTE=0) different divider moduli as it attempts to acquire lock. In this mode, the SS[2:0] pins are outputs and indicate the current value of the divider moduli according to Table 2. Note that for SMPTE = 0 and divider moduli of 2 and 4, the PLL can correctly lock for two values of SS[2:0].
TABLE 2: Data Rate Indication in Auto Mode AUTO/MAN = 1 (Auto Mode) H, L = VCO center frequency as per Figure 12
GS9035A
VLF
A Tcycle Tcycle = tswp + tsys
SMPTE 1 1 1 1 1 1 1 1 0 0 0 0
SS[2:0] 000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111
DIVIDER MODULI 4 2 2 1 1 4 4 2 2 1 -
PLL CLOCK H/4 L/2 H/2 L H H/4 H/4 H/2 H/2 H -
Fig. 13 Typical Sweep Form
The VCO frequency starts at point A and sweeps up attempting to lock. If lock is not established during the up sweep, the VCO is then swept down. The system is designed such that the probability of locking within one cycle period is greater than 0.999. If the system does not lock within one cycle period, it will attempt to lock in the subsequent cycle. In manual mode, the divider modulus is fixed for all cycles. In auto mode, each subsequent cycle is based on a different divider moduli as determined by the internal 3-bit counter. The average sweep time, tswp, is determined by the loop filter component, CLF1, and the charge pump current, CP:
tswp
4 CLF1 = 3 LF1
[seconds]
0 0
The nominal sweep time is approximately 121s when CLF1 = 15nF and CP = 165A (RVCO = 365). An internal system clock determines tsys (see section 7, Logic Circuit).
3. LOGIC CIRCUIT
0 0
4.2 Manual Mode (AUTO/MAN = 0)
The GS9035A is controlled by a finite state logic circuit which is clocked by an asynchronous system clock. That is, the system clock is completely independent of the incoming data rate. The system clock runs at low frequencies, relative to the incoming data rate, and thus reduces interference to the PLL. The period of the system clock is set by the COSC capacitor and is tsys = 9.6 x 104 x COSC [seconds]
In manual mode, the GS9035A divider moduli is fixed. In this mode, the SS[2:0] pins are inputs and set the divider moduli according to Table 3.
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5.1 Lock Time TABLE 3: Data Rate Select in Manual Mode AUTO/MAN = 0 (Manual Mode) H, L = VCO center frequency as per Figure 8 SMPTE 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 SS[2:0] 000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111 DIVIDER MODULI 4 2 2 1 1 8 8 4 4 2 2 1 1 8 PLL CLOCK H/4 L/2 H/2 L H L/8 H/8 H/4 H/4 H/2 H/2 H H H/8 SWITCHING TIME <0.5s 0.5s - 10ms > 10ms LOCK TIME 10s 2tsys 2Tcycle + 2tsys
The lock time of the GS9035A depends on whether the input data is switching synchronously or asynchronously. Synchronous switching refers to the case where the input data is changed from one source to another source which is at the same data rate (but different phase). Asynchronous switching refers to the case where the input data to the GS9035A is changed from one source to another source which is at a different data rate. When input data to the GS9035A is removed, the GS9035A latches the current state of the counter (divider modulus). Therefore, when data is reapplied, the GS9035A begins the lock procedure at the previous locked data rate. As a result, in synchronous switching applications, the GS9035A locks very quickly. The nominal lock time depends on the switching time and is summarized in the table below:
TABLE 4: Lock Time Relative to Switching Time
GS9035A
5. LOCKING
The GS9035A indicates lock when three conditions are satisfied: 1. Input data is detected. 2. The incoming data signal and the PLL clock are phase locked. 3. The system is not locked to a harmonic. The GS9035A defines the presence of input data when at least one data transition occurs every 1s. The GS9035A assumes that it is NOT locked to a harmonic if the pattern `101' or `010' (in the reclocked data stream) occurs at least once every tsys/3 seconds. Using the recommended component values, this corresponds to approximately 150s. (In an harmonically locked system, all bit cells are double clocked and the above patterns become `110011' and `001100', respectively.)
In asynchronous switching applications (including power up) the lock time is determined by the frequency acquisition circuit as described in section 2, Frequency Acquisition. In manual mode, the frequency acquisition circuit may have to sweep over an entire cycle (depending on initial conditions) to acquire lock resulting in a maximum lock time of 2Tcycle + 2tsys. In auto tune mode, the maximum lock time is 6Tcycle + 2tsys since the frequency acquisition circuit may have to cycle through 5 possible counter states (depending on initial conditions) to acquire lock. The nominal value of Tcycle for the GS9035A operating in a typical SMPTE 259M application is approximately 1.3ms. The GS9035A has a dedicated LOCK output (pin 3) indicating when the device is locked. It should be noted that in synchronous switching applications where the switching time is less than 0.5s, the LOCK output will NOT be de-asserted and the data outputs will NOT be muted.
5.2 DVB-ASI
Design Note: For DVB-ASI applications having significant instances of few bit transitions or when only K28.5 idle bits are transmitted, the wide-band PLL in the GS9035A may lock at 243MHz being the first 27MHz sideband below 270MHz. In this case, when normal bit density signals are transmitted, the PLL will correctly lock onto the proper 270MHz carrier.
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6. OUTPUT DATA MUTING
The GS9035A internally mutes the SDO and SDO outputs when the device is not locked. When muted, SDO/SDO are latched providing a logic state to the subsequent circuit and avoiding a condition where noise could be amplified and appear as data. The output data muting timing is shown in Figure 14.
DDI NO DATA TRANSITIONS
PHASE DETECTOR Oi
+
KPD
-
CP
VCO 2Kf Ns
Oo
LOOP FILTER
RLF CLF1 CLF2
GS9035A
LOCK
Fig. 15 PLL Model 9.1 Transfer Function
SDO
VALID DATA
OUTPUTS MUTED
VALID DATA
The transfer function of the PLL is defined as Oo/Oi and can be approximated as sC LF1 R LF + 1 Oo 1 ------ = --------------------------------------------------------------- --------------------------------------------------------L L - + 1 2 Oi C s LF1 R LF - --------s C LF2 L + s -------- + 1 R LF R LF
Equation 1
Fig. 14 Output Data Muting Timing 7. CLOCK ENABLE
When CLK_EN is high, the GS9035A SCO/SCO outputs are enabled. When CLK_EN is low, the SCO/SCO outputs are set to a high Z state and float to VCC. Disabling the clock outputs results in a power savings of 10%. It is recommended that the CLK_EN input be hard wired to the desired state. For applications which do not require the clock output, connect CLK_EN to Ground and connect the SCO/SCO outputs to VCC.
8. STRESSFUL DATA PATTERNS
where NL = ------------------DI CP K N is the divider modulus D is the data density (=0.5 for NRZ data)
All PLL's are susceptible to stressful data patterns which can introduce bit errors in the data stream. PLL's are most sensitive to patterns which have long run lengths of zeros or ones (low data transition densities for a long period of time). The GS9035A is designed to operate with low data transition densities such as the SMPTE 259M pathological signal (data transition density = 0.05).
9. PLL DESIGN GUIDELINES
CP is the charge pump current in Amps K is the VCO gain in Hz/V This response has 1 zero (wZ) and three poles (wP1, wBW, wP2) where 1w Z = ---------------------C LF1 R LF 1 w P1 = -------------------------------------L C LF1 R LF - --------R LF R LF w BW = --------L 1w P2 = ---------------------C LF2 R LF The bode plot for this transfer function is plotted in Figure 16.
The performance of the GS9035A is primarily determined by the PLL. Thus, it is important that the system designer is familiar with the basic PLL design equations. A model of the GS9035A PLL is shown below. The main components are the phase detector, the VCO, and the external loop filter components.
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The second is the zero-pole combination:
0
AMPLITUDE (dB)
s ------ + 1 sC LF1 R LF + 1 wZ ---------------------------------------------------------- = ------------------sL--------- + 1 s C LF1 R LF - ---------- + 1 w P1 R LF This causes lift in the transfer function given by w P1 1 20 LOG --------- = 20 LOG --------------------wZ wZ 1 - ----------w BW
WZ WP1 FREQUENCY WBW WP2
GS9035A
To keep peaking to less than 0.05dB, wZ < 0.0057 wBW
9.3 Selection of Loop Filter Components
Fig. 16 Bode Plot for PLL Transfer Function
The 3dB bandwidth of the transfer function is approximately w 3dB w BW w BW = --------------------------------------------------------------------- ----------0.78 w BW ( w BW w P2 ) 2 1 - 2 ----------- + --------------------------------w P2 w BW ----------1-2 w P2
Based on the above analysis, select the loop filter components for a given PLL bandwidth, 3dB, as follows: 1. Calculate where CP is the charge pump current and is a function of the RVCO resistor and is obtained from Figure 17. K = 90MHz/V for VCO frequencies corresponding to the L curve. K = 140MHz/V for VCO frequencies corresponding to the H curve. N is the divider modulus. (L, H and N can be obtained from Table 2 or Table 3).
9.2 Transfer Function Peaking
There are two causes of peaking in the PLL transfer function given by Equation 1. The first is the quadratic L s C LF2 L + s --------- + 1 R LF
2
which has 1 w O = -------------------C LF2 L C LF2 Q = R LF -----------L and
2. Choose RLF = 2(3.14) 3dB (0.78)L 3. Choose CLF1 = 174 L / (RLF) 4. Choose CLF2 = L/4(RLF)2
400
2
This response is critically damped for Q = 0.5. Thus, to avoid peaking: C LF2 1 R LF ------------ < --2 L or 1 - L---------------------- -------- > 4 R LF C LF2 R LF Therefore, wP2 > 4 wBW
CHARGE PUMP CURRENT (A)
350 300 250 200 150 100 50 0 0 200 400 600 800 1000 1200 1400 1600 1800
L=
CPK
2N
However, it is desirable to keep wP2 as low as possible to reduce the high frequency content on the loop filter.
RVCO ()
Fig. 17 Charge Pump Current vs. RVCO
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9.4 Spice Simulations
1. Input signal amplitudes are between 200 and 2000mV 2. The common mode input voltage range is as specified in the DC Characteristics table. Commonly used interface Figures 19 and 20. examples are shown in
More detailed analysis of the GS9035A PLL can be done using SPICE. A SPICE model of the PLL is shown below:
PHII IN+ INRLF 1 CLF1 R2
G1 LF PHIO E1 2K Ns
V1
CLF2
NOTE: PHII, PHIO, LF and 1 are node names in the SPICE netlist.
Figure 19 illustrates the simplest interface to the GS9035A. In this example, the driving device generates the PECL level signals (800mV amplitudes) having a common mode input range between 0.4 and 4.6V. This scheme is recommended when the trace lengths are less than 1in. The value of the resistors and the DC connection (VCC or Ground), depends on the output driver circuitry of the previous device.
VCC or GND
GS9035A
Fig. 18 SPICE Model of PLL
The model consists of a voltage controlled current source (G1), the loop filter components (RLF, CLF1, and CLF2), a voltage controlled voltage source (E1), and a voltage source (V1). R2 is necessary to create a DC path to ground for Node 1. V1 is used to generate the input phase waveform. G1 compares the input and output phase waveforms and generates the charge pump current, CP. The loop filter components integrate the charge pump current to establish the loop filter voltage. E1 creates the output phase waveform (PHIO) by multiplying the loop filter voltage by the value of the Laplace transform (2pK/Ns). The netlist for the model is given below. The .PARAM statements are used to set values for CP, K, N, and D. CP is determined by the RVCO resistor and is obtained from Figure 17. SPICE NETLIST * GS9035A PLL Model .PARAM ICP = 165E-6 KF= 90E+6 .PARAM N = 1 D = 0.5 .PARAM PI = 3.14 .IC V(Phio) = 0 .ac dec 30 1k 10meg RLF 1 LF 1000 CLF1 1 0 15n CLF2 0 LF 15p E_LAPLACE1 Phio 0 LAPLACE {V(LF)} {(2*PI*KF)/(N*s)} G1 0 LF VALUE{D * ICP/(2*pi)*V(Phii, Phio)} V1 2 0 DC 0V AC 1V R2 0 1 1g .END
10. I/O DESCRIPTION 10.1 High Speed Inputs (DDI/DDI)
DDI GS9035A DDI
VCC or GND
Fig. 19 Simple Interface to the GS9035A
When trace lengths become greater than 1in, controlled impedance traces should be used. The recommended interface for differential signals is shown in Figure 20. In this case, a parallel resistor (RLOAD) is placed near the GS9035A inputs to terminate the controlled impedance trace. The value of RLOAD should be twice the value of the characteristic impedance of the trace. Both traces should be in a symmetric arrangement and same physical transmission line dimensions since common-mode signals or common-mode noise is not terminated. In addition, series resistors, RSOURCE, can be placed near the driving chip to serve as source terminations. They should be equal to the value of the trace impedance. Assuming 800mV output swings at the driver, RLOAD =100, RSOURCE =50 and ZO = 50.
RSOURCE RSOURCE ZO ZO DDI RLOAD DDI GS9035A
Fig. 20 Recommended Interface for Differential Signals
DDI/DDI are high impedance inputs which accept differential or single-ended input drive. Two conditions must be observed when interfacing to these inputs:
Figure 21 shows the recommended interface when the GS9035A is driven single-endedly. In this case, the input must be AC-coupled and a matching resistor (ZO) must be used.
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DDI ZO DDI GS9035A VCC
Fig. 21 Recommended Interface for Single-Ended Driver 10.2 High Speed Outputs (SDO/SDO and SCO/SCO)
75 SDO SDO SCO SCO 75 75 75
GS9035A
SDO/SDO and SCO/SCO are current mode outputs that require external pullup resistors (see Figure 22). To calculate the output sink current use the following relationship: Output Sink Current = Output Signal Swing / Pullup Resistor A diode can be placed between Vcc and the pullup resistors to reduce the common mode voltage by approximately 0.7 volts.When the output traces are longer than 1in, controlled impedance traces should be used. The pullup resistors should be placed at the end of the output traces as they terminate the trace in its characteristic impedance (75). TYPICAL APPLICATION CIRCUIT
GS9035A
VCC
Fig. 22 High Speed Outputs with External Pullups
The figure below shows the GS9035A connected in a typical auto rate select SMPTE 259M application. Table 4 summarizes the relevant system parameters.
VCC VCC 4 SMPTE 3 LOCK 10k 4.7n 2 COSC 1 VEE VCC VCC VCC VCC
28 CLK_EN
27 VEE
26 VCC3 4 x 75 SDO 25
From GS9024
5
DDI
6
DDI
SDO 24 To GS90201
7
VEE VEE VCC1 AUTO/MAN RVCO_RTN GS9035A TOP VIEW
SCO 23
8
SCO 22
VCC VCC
9
SSO 21
10
SS1 20
RVCO
All resistors in ohms, all capacitors in farads, unless otherwise shown. Power supply decoupling capacitors are not shown. See application note "EB9035A" for details on PCB artwork.
12 RLF 1800
13 CLF1 15n
14
15 RVCO
16 365 (1%)
17 0.1
18
VCC2
CBG
11
LFS
LF+
VEE
SS2 19
}
To LED Driver (optional)
LF-
NOTE 1. The 75 pullup resistors on SDO/SDO and SCO/SCO are not required when interfacing the GS9035A to the GS9020 since the GS9020 has internal 75 resistors.
CLF2 3.3p
0.1 VCC
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TABLE 5: System Parameters RVCO = 365, H = 540MHz, L = 360MHz SMPTE 1 1 1 1 1 SS[2:0] 000 001 010 011 100 DATA RATE (Mb/s) 143 177 270 360 540 LOOP BANDWIDTH 1.2MHz 1.9MHz
GS9035A
3.0MHz 4.5MHz 6.0MHz
PACKAGE DIMENSIONS
12.573 MAX 12.319 MIN 1.219 x 45 1.067 11.582 MAX 11.430 MIN
SEATING PLANE MIN 0.508
1.270
12.573 MAX 12.319 MIN 11.582 MAX 11.430 MIN
10.922 MAX 9.906 MIN
3.048 MAX 2.286 MIN 4.572 MAX 4.115 MIN
All dimensions in millimetres. 28 pin PLCC (QM)
CAUTION
ELECTROSTATIC SENSITIVE DEVICES
DO NOT OPEN PACKAGES OR HANDLE EXCEPT AT A STATIC-FREE WORKSTATION
DOCUMENT IDENTIFICATION
DATA SHEET The product is in production. Gennum reserves the right to make changes at any time to improve reliability, function or design, in order to provide the best product possible.
REVISION NOTES:
Added lead-free and green information. For latest product information, visit www.gennum.com
GENNUM CORPORATION
MAILING ADDRESS: P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3 Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 SHIPPING ADDRESS: 970 Fraser Drive, Burlington, Ontario, Canada L7L 5P5
GENNUM JAPAN CORPORATION Shinjuku Green Tower Building 27F, 6-14-1, Nishi Shinjuku, Shinjuku-ku, Tokyo, 160-0023 Japan Tel. +81 (03) 3349-5501, Fax. +81 (03) 3349-5505 GENNUM UK LIMITED 25 Long Garden Walk, Farnham, Surrey, England GU9 7HX Tel. +44 (0)1252 747 000 Fax +44 (0)1252 726 523
Gennum Corporation assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement. (c) Copyright July 1999 Gennum Corporation. All rights reserved. Printed in Canada.
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